1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same, and more particularly to a semiconductor device having a super junction structure with p-type pillars and n-type pillars formed laterally, periodically and alternately in a drift layer, and method of manufacturing the device.
2. Description of the Related Art
A vertical power MOSFET has an on-resistance greatly dependent on the electrical resistance in a conduction layer (drift layer) thereof. The electrical resistance in the drift layer is determined from its impurity concentration, and the on-resistance can be lowered as the impurity concentration is made higher. A higher impurity concentration, however, lowers the breakdown voltage across a PN junction formed by the drift layer together with a base layer. Accordingly, the impurity concentration can not be made higher than the limit determined in accordance with the breakdown voltage. Thus, there is a tradeoff between the device breakdown voltage and the on-resistance. An improvement in tradeoff is one important subject matter to provide a semiconductor device of low power dissipation. The tradeoff has a limit determined from device material, and exceeding the limit is a way to realize a low-on-resistance semiconductor device.
As an example of the MOSFET to solve the problem, there is a known structure, which is referred to as a superjunction structure with p-type pillar layers and n-type pillar layers buried in a drift layer laterally and alternately. In the superjunction structure, the quantities of charges (the quantities of impurities) contained in the p-type pillar layers and the n-type pillar layers are equalized to artificially create a non-doped layer. This is effective to retain a high breakdown voltage and cause a current flowing through highly doped, n-type pillar layers, thereby realizing a low on-resistance that exceeds the material limit.
A superjunction structured MOSFET can be given a higher device breakdown voltage as the superjunction structure has a larger thickness. The larger thickness, however, complicates the process steps correspondingly.
It is effective on the other hand in the superjunction structured MOSFET to narrow a lateral period (pitch) of the superjunction structure to achieve a further reduced on-resistance. A narrower width facilitates a p-n junction to deplete on non-conduction and correspondingly it makes it possible to increase the impurity concentration in a pillar layer.
If PN pillars have a cell pitch of 5 μm, achievement of a breakdown voltage of 300 V requires the pillar layer of the superjunction structure to have a thickness of about 17 μm. When the P pillar occupies one half of the cell pitch, the P pillar should be formed to have an aspect ratio of about 6-8. Such the narrow-width and high-aspect-ratio pillar layer may be formed in the following manufacturing method. This method comprises forming a deep trench below the surface of an epitaxial layer, and burying a semiconductor of a different conduction type in the trench by epitaxial growth (see JP-A 2004-14554).
Another manufacturing method comprises forming a buried layer selectively in a high-resistance epitaxial layer by ion implantation and diffusion, and additionally stacking a high-resistance epitaxial layer thereon to form a buried layer by ion implantation and diffusion in the same manner as in the lower layer. These steps are repeated several times (see JP-A 2000-40822). In this case, each high-resistance epitaxial layer should be formed to have a thickness enough to connect the vertically located n-type and p-type diffusion layers. Accordingly, achievement of a high aspect ratio requires a longer diffusion time or an increase in the number of steps of epitaxial growth and ion implantation.